While Von Neumann has only an accumulator, MIPS has 32 registers
Prefixes:
R#: Register
M#: Memory
Control Unit: All computer operations are controlled by the CU.
Timing signals that govern the IO transfers and generated by the CU
Usually distributed throughout the machine, not just a single unit
ALU: Most computer operations are executed in the processor’s ALUExample: Data flow in and out of the ALU
Load operands into memory
Bring operands from memory into the processor’s registers
Perform operation in ALU
Store result in the processor or move back into memory
Memory Unit
Memory Unit: Stores programs and data
Main Memory: Volatile
Fast.
Processed in words (e.g., 4 bits at a time)
Secondary Storage: Non-volatile
Larger and cheaper.
Basic Operational Concepts
To perform tasks, we use programs (lists of instructions and data), which are stored in memory, which are moved into the processor’s registers and/or cache as needed.Example: A Typical Instruction
ADD R0, M1
What it does: R0 <- R0 + M1
M1’s contents are preserved.
R0 is overwritten.
Note: The leftmost operand is the destination
Note: In the real world, the BIU is accessible only to the control unit, and the IR and PC are only indirectly accessible through instructions.
Example: Typical Operating Steps
\text{Program Execution: } \\
\text{Secondary Storage $\to$ Main Memory $\to$ CPU Registers $\to$ Execution}
Program loaded from secondary storage into main memory.
Done by the loader
PC set to point to the first instruction.
Content of PC is transferred to the MAR
Read signal is asserted to main memory
Instruction retrieved from memory and loaded into MDR
Contents of MDR transferred to IR
(This is necessary for the decode cycle to start.)
Instruction get decoded by CU.
Get operands for the ALU
Operands can be in the general-purpose registers or in memory.
Note: Some instructions don’t use ALU
e.g., Loading & storing memory and interrupt instructions don’t use ALU
Perform operations using ALU
Store result
Can be stored in a general-purpose register or memory.
PC incremented to next step
(Hardware-wise, this is conditional (example: doesn’t happen on jump instructions))